1. Field
Embodiments of the present invention generally relate to methods of forming high aspect ratio features in a vertical type semiconductor device, and more particularly to methods of forming high aspect ratio features in a vertical type semiconductor device with stair-like structures for semiconductor applications.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI interconnect technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
A patterned mask, such as a photoresist layer, is commonly used in forming structures, such as gate structure, shallow trench isolation (STI), bite lines and the like, on a substrate by etch process. The patterned mask is conventionally fabricated by using a lithographic process to optically transfer a pattern having the desired critical dimensions to a layer of photoresist. The photoresist layer is then developed to remove undesired portion of the photoresist, thereby creating openings in the remaining photoresist.
In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Three dimensional (3D) stacking of semiconductor chips reduces wire lengths and keeps wiring delay low. In manufacturing three dimensional (3D) stacking of semiconductor chips, stair-like structures are often utilized to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices.
When forming features, such as trenches or vias, in stair-like structures in a film stack disposed on a substrate, an etch process using a photoresist layer as an etching mask is often utilized. The film stack comprises multiple material layers in which the features, such as trenches or vias, are formed with high aspect ratios. High aspect ratio is generally defined as the ratio between the depth of the feature and the width of the feature, for at least about 20:1 and greater. In an exemplary embodiment depicted in FIG. 1A, a photoresist layer (not shown) may serve as an etching mask layer to transfer structures onto a film stack 100 disposed on a substrate 104 to form stair-like structures 110 on the substrate 104. The film stack 100 typically includes alternating layers of layers 102a, 102b (shown as 102a1, 102b1, 102a2, 102b2, . . . , 102n1, 102n2), either conductive layers or insulating layers. During etching, features 130 with high aspect ratio, such as greater than 20:1, may be formed into the film stack 100.
During etching of features 130, 132, 134 into the film stack 100 on the substrate 104, redeposition or build-up of by-products or other materials generated during the etch process may accumulate and/or attack on the top and/or sidewalls of the features 130, 132, 134 being etched, thereby blocking the opening the feature 130, 132, 134 being formed in the film stack 100. For example, the redeposition or build-up of by-products during etch process may result in early close-up of the feature, such as one of the exemplary features 132 depicted in FIG. 1A, thus preventing etching through the entire film stack 100 to expose the substrate 104. As the opening of the etched features 132 are narrowed and/or sealed by the accumulated redeposition material, the reactive etchants are prevented from reaching the lower surface 133 of the features 132, thereby limiting the aspect ratio that may be obtained. The feature 130 formed in the film stack 100 represents a good example in which a desired profile and dimension formed in the feature 130 has been obtained, e.g., with the features 130 formed through the film stack 100 reach a desired depth in the substrate 104 without significant top surface or features sidewall loss.
Furthermore, irregular profiles and growth of the etching by-products formed during etching may gradually block the small openings used to fabricate the small critical dimension structures, thereby resulting in bowed, distorted, toppled, or twisted profiles of the etched structures. FIG. 1B depicts an example of a magnified view of a defective feature 134 circled in FIG. 1A. Redeposition material 138 or build-up of etching by-products may be randomly and/or irregularly adhere to the top surface 139 and/or sidewalls 140 of the film stack 100, the resulting irregular profile and growth of the redeposition material 138 or etching by-products may alter the flow path of the reactive etchants, resulting in a bowing or twisting profile 142 of the features 134 formed in the film stack 100. As the film stack 100 formed on the substrate 104 often includes one or more different materials, such as materials 102a and 102b, poor profile control or edge line discontinuity at the interface of different materials may result in incompatible stress between each film. As the geometry and the aspect ratio of the structures become even smaller and higher, the stress mismatch issue occurred between different materials in the film stack become increasingly dominant, thereby resulting in stress induced line edge roughness or line breakage, eventually resulting in device failure.
Thus, there is a need for improved methods and apparatus for forming high aspect ratio features, such as forming features in stair-like structures, with accurate profiles and dimension control for three dimensional (3D) stacking of semiconductor chips.